Advanced Bayer demosaicing on FPGAs

Donald Bailey, Sharmil Randhawa, Jim S.Jimmy Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Citations (Scopus)

Abstract

Demosaicing is the process of interpolating the output from a single chip colour filter array sensor to form a full colour image. In hardware, the simplest algorithms: zero order hold and bilinear interpolation, are commonly used because of their simplicity and low resource requirements. State of the art algorithms are difficult to implement in hardware because of their complex access patterns. This paper explores the streamed implementation of a higher order interpolation filter, with a weighted median classifier. Although this comes at a cost of a factor of 10 increase in hardware resources, and a reduction in maximum pixel clock frequency by 30%, this state of the art algorithm gives considerably improved images of 11.2 dB in peak signal to noise ratio with a considerable reduction in interpolation artifacts. For real-Time applications where image quality is critical, an implementation of such an advanced demosaicing algorithm on FPGA is essential.

Original languageEnglish
Title of host publication2015 International Conference on Field Programmable Technology, FPT 2015
Subtitle of host publicationFPT 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages216-220
Number of pages5
ISBN (Electronic)9781467390910
DOIs
Publication statusPublished - 25 Jan 2016
EventInternational Conference on Field Programmable Technology, FPT 2015 - Queenstown, New Zealand
Duration: 7 Dec 20159 Dec 2015

Publication series

Name2015 International Conference on Field Programmable Technology, FPT 2015

Conference

ConferenceInternational Conference on Field Programmable Technology, FPT 2015
CountryNew Zealand
CityQueenstown
Period7/12/159/12/15

Keywords

  • Bayer pattern
  • colour filter array
  • demosaicing
  • higher order interpolation
  • stream processing

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