CMOS compatible integrated ferroelectric tunnel junctions (FTJ)

Mohammad Abuwasib; Hyungwoo Lee; Pankaj Sharma; Chang-Beom Eom; Alexei Gruverman; Uttam Singisetti

doi:10.1109/DRC.2015.7175545

CMOS compatible integrated ferroelectric tunnel junctions (FTJ)

Mohammad Abuwasib, Hyungwoo Lee, Pankaj Sharma, Chang-Beom Eom, Alexei Gruverman, Uttam Singisetti

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

As traditional CMOS scaling reaches fundamental limits, there is an increasing interest in non-charge based beyond CMOS devices that could increase the functionality of logic chips [1]. Ferroelectric tunnel junction (FTJ) devices are attractive due to their large ON/OFF ratios, non-volatile, and low energy operation [2]. Switching has been demonstrated in the metal-ferroelectric-metal (M-F-M) FTJs in non-integrated devices that use the conductive atomic force microscope (AFM) tip as an electrode [3-4]. However, it is necessary to investigate the CMOS compatibility, scalability, switching speed and switching dynamics in an integrated FTJ device. We report a CMOS compatible integrated FTJ fabrication process that is scalable from micron to deep submicron dimensions. The first generation integrated FTJs show switching with peak ON/OFF ratio of 60. We also report the scalability of the ferroelectric polarization loop to 550 nm × 550 nm device. Conductivity degradation of the La_xSr_1-xMnO₃ (LSMO) bottom conductor is observed due to reactive ion etch (RIE) process that impacts device performance.

Original language	English
Title of host publication	73rd Annual Device Research Conference, DRC 2015
Publisher	Institute of Electrical and Electronics Engineers
Pages	45-46
Number of pages	2
ISBN (Electronic)	9781467381345
DOIs	https://doi.org/10.1109/DRC.2015.7175545
Publication status	Published - 3 Aug 2015
Externally published	Yes
Event	73rd Annual Device Research Conference, DRC 2015 - Columbus, United States Duration: 21 Jun 2015 → 24 Jun 2015

Publication series

Name	Device Research Conference - Conference Digest, DRC
Volume	2015-August
ISSN (Print)	1548-3770

Conference

Conference	73rd Annual Device Research Conference, DRC 2015
Country/Territory	United States
City	Columbus
Period	21/06/15 → 24/06/15

Keywords

CMOS integrated circuits
Force
Gold
Lead
Resistance
Switching circuits

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10.1109/DRC.2015.7175545Licence: In Copyright

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Abuwasib, M., Lee, H., Sharma, P., Eom, C.-B., Gruverman, A., & Singisetti, U. (2015). CMOS compatible integrated ferroelectric tunnel junctions (FTJ). In 73rd Annual Device Research Conference, DRC 2015 (pp. 45-46). Article 7175545 (Device Research Conference - Conference Digest, DRC; Vol. 2015-August). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/DRC.2015.7175545

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title = "CMOS compatible integrated ferroelectric tunnel junctions (FTJ)",

abstract = "As traditional CMOS scaling reaches fundamental limits, there is an increasing interest in non-charge based beyond CMOS devices that could increase the functionality of logic chips [1]. Ferroelectric tunnel junction (FTJ) devices are attractive due to their large ON/OFF ratios, non-volatile, and low energy operation [2]. Switching has been demonstrated in the metal-ferroelectric-metal (M-F-M) FTJs in non-integrated devices that use the conductive atomic force microscope (AFM) tip as an electrode [3-4]. However, it is necessary to investigate the CMOS compatibility, scalability, switching speed and switching dynamics in an integrated FTJ device. We report a CMOS compatible integrated FTJ fabrication process that is scalable from micron to deep submicron dimensions. The first generation integrated FTJs show switching with peak ON/OFF ratio of 60. We also report the scalability of the ferroelectric polarization loop to 550 nm × 550 nm device. Conductivity degradation of the LaxSr1-xMnO3 (LSMO) bottom conductor is observed due to reactive ion etch (RIE) process that impacts device performance.",

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author = "Mohammad Abuwasib and Hyungwoo Lee and Pankaj Sharma and Chang-Beom Eom and Alexei Gruverman and Uttam Singisetti",

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doi = "10.1109/DRC.2015.7175545",

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Abuwasib, M, Lee, H, Sharma, P, Eom, C-B, Gruverman, A & Singisetti, U 2015, CMOS compatible integrated ferroelectric tunnel junctions (FTJ). in 73rd Annual Device Research Conference, DRC 2015., 7175545, Device Research Conference - Conference Digest, DRC, vol. 2015-August, Institute of Electrical and Electronics Engineers, pp. 45-46, 73rd Annual Device Research Conference, DRC 2015, Columbus, United States, 21/06/15. https://doi.org/10.1109/DRC.2015.7175545

CMOS compatible integrated ferroelectric tunnel junctions (FTJ). / Abuwasib, Mohammad; Lee, Hyungwoo; Sharma, Pankaj et al.
73rd Annual Device Research Conference, DRC 2015. Institute of Electrical and Electronics Engineers, 2015. p. 45-46 7175545 (Device Research Conference - Conference Digest, DRC; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - CMOS compatible integrated ferroelectric tunnel junctions (FTJ)

AU - Abuwasib, Mohammad

AU - Lee, Hyungwoo

AU - Sharma, Pankaj

AU - Eom, Chang-Beom

AU - Gruverman, Alexei

AU - Singisetti, Uttam

PY - 2015/8/3

Y1 - 2015/8/3

N2 - As traditional CMOS scaling reaches fundamental limits, there is an increasing interest in non-charge based beyond CMOS devices that could increase the functionality of logic chips [1]. Ferroelectric tunnel junction (FTJ) devices are attractive due to their large ON/OFF ratios, non-volatile, and low energy operation [2]. Switching has been demonstrated in the metal-ferroelectric-metal (M-F-M) FTJs in non-integrated devices that use the conductive atomic force microscope (AFM) tip as an electrode [3-4]. However, it is necessary to investigate the CMOS compatibility, scalability, switching speed and switching dynamics in an integrated FTJ device. We report a CMOS compatible integrated FTJ fabrication process that is scalable from micron to deep submicron dimensions. The first generation integrated FTJs show switching with peak ON/OFF ratio of 60. We also report the scalability of the ferroelectric polarization loop to 550 nm × 550 nm device. Conductivity degradation of the LaxSr1-xMnO3 (LSMO) bottom conductor is observed due to reactive ion etch (RIE) process that impacts device performance.

AB - As traditional CMOS scaling reaches fundamental limits, there is an increasing interest in non-charge based beyond CMOS devices that could increase the functionality of logic chips [1]. Ferroelectric tunnel junction (FTJ) devices are attractive due to their large ON/OFF ratios, non-volatile, and low energy operation [2]. Switching has been demonstrated in the metal-ferroelectric-metal (M-F-M) FTJs in non-integrated devices that use the conductive atomic force microscope (AFM) tip as an electrode [3-4]. However, it is necessary to investigate the CMOS compatibility, scalability, switching speed and switching dynamics in an integrated FTJ device. We report a CMOS compatible integrated FTJ fabrication process that is scalable from micron to deep submicron dimensions. The first generation integrated FTJs show switching with peak ON/OFF ratio of 60. We also report the scalability of the ferroelectric polarization loop to 550 nm × 550 nm device. Conductivity degradation of the LaxSr1-xMnO3 (LSMO) bottom conductor is observed due to reactive ion etch (RIE) process that impacts device performance.

KW - CMOS integrated circuits

KW - Force

KW - Gold

KW - Lead

KW - Resistance

KW - Switching circuits

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BT - 73rd Annual Device Research Conference, DRC 2015

PB - Institute of Electrical and Electronics Engineers

T2 - 73rd Annual Device Research Conference, DRC 2015

Y2 - 21 June 2015 through 24 June 2015

ER -

CMOS compatible integrated ferroelectric tunnel junctions (FTJ)

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Keywords

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