TY - GEN
T1 - FPGA implementation of a parameterized Fourier synthesizer
AU - Yang, R.
AU - Wang, J. G.
AU - Clement, B.
AU - Mansour, A.
PY - 2014/5/15
Y1 - 2014/5/15
N2 - Field-Programmable Gate Array (FPGA) offers advantages for many applications, particularly where missions are complex and time performance is critical. For small-production digital acoustic synthesizers, FPGA can achieve the above-mentioned tighter system requirements with low total system costs on single chip. In this manuscript, a real-time acoustic synthesizer is implemented using Fourier series algorithm on Altera's Cyclone II FPGA chip. This work emphasizes systematic designs and parallel computations. The proposed system includes a flexible processor and a parallel parameterized acoustic module. On one hand, the Nios II embedded processor, which is relatively low-speed component, is used to generate commands and configure high-speed acoustic module parameters. On the other hand, acoustic module which should require high-speed components contains 4 parallel architectures to gain high-speed simultaneous calculus of 4 independent digital timbres. Every timbre is equivalent to 16 parallel high-precision harmonic channels with 0.3 % frequency error. Experimental results corroborate the fact that a single FPGA chip can achieve complex missions and attain real-time performances.
AB - Field-Programmable Gate Array (FPGA) offers advantages for many applications, particularly where missions are complex and time performance is critical. For small-production digital acoustic synthesizers, FPGA can achieve the above-mentioned tighter system requirements with low total system costs on single chip. In this manuscript, a real-time acoustic synthesizer is implemented using Fourier series algorithm on Altera's Cyclone II FPGA chip. This work emphasizes systematic designs and parallel computations. The proposed system includes a flexible processor and a parallel parameterized acoustic module. On one hand, the Nios II embedded processor, which is relatively low-speed component, is used to generate commands and configure high-speed acoustic module parameters. On the other hand, acoustic module which should require high-speed components contains 4 parallel architectures to gain high-speed simultaneous calculus of 4 independent digital timbres. Every timbre is equivalent to 16 parallel high-precision harmonic channels with 0.3 % frequency error. Experimental results corroborate the fact that a single FPGA chip can achieve complex missions and attain real-time performances.
UR - http://www.scopus.com/inward/record.url?scp=84901463039&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2013.6815457
DO - 10.1109/ICECS.2013.6815457
M3 - Conference contribution
AN - SCOPUS:84901463039
SN - 9781479924523
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 473
EP - 476
BT - 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Y2 - 8 December 2013 through 11 December 2013
ER -