Implementation and Optimization of the OpenMP Accelerator Model for the TI Keystone II Architecture

Gaurav Mitra, Eric Stotzer, Ajay Jayaraj, Alistair Rendell

Research output: Contribution to journalArticlepeer-review

22 Citations (Scopus)


The TI Keystone II architecture provides a unique combination of ARM Cortex-A15 processors with high performance TI C66x floating-point DSPs on a single low-power System-on-chip (SoC). Commercially available systems such as the HP Proliant m800 and nCore BrownDwarf are based on this ARM-DSP SoC. The Keystone II architecture promises to deliver high GFLOPS/Watt and is of increasing interest as it provides an alternate building block for future exascale systems. However, the success of this architecture is intimately related to the ease of migrating existing HPC applications for maximum performance. Effective use of all ARM and DSP cores and DMA co-processors is crucial for maximizing performance/watt. This paper explores issues and challenges encountered while migrating the matrix multiplication (GEMM) kernel, originally written only for the C6678 DSP to the ARM-DSP SoC using an early prototype of the OpenMP 4.0 accelerator model. Single precision (SGEMM) matrix multiplication performance of 110.11 GFLOPS and and double precision (DGEMM) performance of 29.15 GFLOPS was achieved on the TI Keystone II Evaluation Module Revision 3.0 (EVM). Trade-offs and factors affecting performance are discussed.

Original languageEnglish
Pages (from-to)202-214
Number of pages13
JournalLecture Notes in Computer Science
Publication statusPublished - 2014
Externally publishedYes
EventInternational Workshop on OpenMP, IWOMP 2014 - Salvadore, Brazil
Duration: 28 Sep 201430 Sep 2014
Conference number: 10


  • Graphic Processing Unit
  • Target Device
  • Scratchpad Memor
  • OpenCL Kernel
  • Memory Management Uni


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