Implementation of square-root and exponential functions for large FPGAs

Mariusz Bajger; Amos Omondi

doi:10.1007/11859802_3

Implementation of square-root and exponential functions for large FPGAs

Mariusz Bajger, Amos Omondi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

This paper discusses low-error, high-speed evaluation of two elementary functions: square-root (which is required in IEEE-754 standard on computer arithmetic) and exponential (which is common in scientific calculations). The basis of the proposed implementations is piecewise-linear interpolation but with the constants chosen in a way that minimizes relative error. We show that by placing certain constraints on the errors at three points within each interpolation interval, relative errors are greatly reduced. The implementation-targets are large FPGAs that have in-built multipliers, adders, and distributed memory.

Original language	English
Title of host publication	Advances in Computer Systems Architecture
Subtitle of host publication	11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings
Editors	Chris Jesshope, Colin Egan
Place of Publication	Berlin
Publisher	Springer
Pages	6-23
Number of pages	18
ISBN (Electronic)	978-3-540-40058-5
ISBN (Print)	978-3-540-40056-1
DOIs	https://doi.org/10.1007/11859802_3
Publication status	Published - Sept 2006
Event	11th Asia-Pacific Conference, Asia-Pacific Conference on Advances in Computer Systems Architecture 2006 - Shanghai, China Duration: 6 Sept 2006 → 8 Sept 2006 Conference number: 11th

Conference

Conference	11th Asia-Pacific Conference, Asia-Pacific Conference on Advances in Computer Systems Architecture 2006
Country/Territory	China
City	Shanghai
Period	6/09/06 → 8/09/06

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Cite this

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title = "Implementation of square-root and exponential functions for large FPGAs",

abstract = "This paper discusses low-error, high-speed evaluation of two elementary functions: square-root (which is required in IEEE-754 standard on computer arithmetic) and exponential (which is common in scientific calculations). The basis of the proposed implementations is piecewise-linear interpolation but with the constants chosen in a way that minimizes relative error. We show that by placing certain constraints on the errors at three points within each interpolation interval, relative errors are greatly reduced. The implementation-targets are large FPGAs that have in-built multipliers, adders, and distributed memory.",

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Bajger, M & Omondi, A 2006, Implementation of square-root and exponential functions for large FPGAs. in C Jesshope & C Egan (eds), Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings. Springer , Berlin, pp. 6-23, 11th Asia-Pacific Conference, Asia-Pacific Conference on Advances in Computer Systems Architecture 2006, Shanghai, China, 6/09/06. https://doi.org/10.1007/11859802_3

Implementation of square-root and exponential functions for large FPGAs. / Bajger, Mariusz; Omondi, Amos.
Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings. ed. / Chris Jesshope; Colin Egan. Berlin: Springer , 2006. p. 6-23.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper discusses low-error, high-speed evaluation of two elementary functions: square-root (which is required in IEEE-754 standard on computer arithmetic) and exponential (which is common in scientific calculations). The basis of the proposed implementations is piecewise-linear interpolation but with the constants chosen in a way that minimizes relative error. We show that by placing certain constraints on the errors at three points within each interpolation interval, relative errors are greatly reduced. The implementation-targets are large FPGAs that have in-built multipliers, adders, and distributed memory.

AB - This paper discusses low-error, high-speed evaluation of two elementary functions: square-root (which is required in IEEE-754 standard on computer arithmetic) and exponential (which is common in scientific calculations). The basis of the proposed implementations is piecewise-linear interpolation but with the constants chosen in a way that minimizes relative error. We show that by placing certain constraints on the errors at three points within each interpolation interval, relative errors are greatly reduced. The implementation-targets are large FPGAs that have in-built multipliers, adders, and distributed memory.

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BT - Advances in Computer Systems Architecture

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Implementation of square-root and exponential functions for large FPGAs

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