Implementation of square-root and exponential functions for large FPGAs

Mariusz Bajger, Amos Omondi

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Citations (Scopus)

    Abstract

    This paper discusses low-error, high-speed evaluation of two elementary functions: square-root (which is required in IEEE-754 standard on computer arithmetic) and exponential (which is common in scientific calculations). The basis of the proposed implementations is piecewise-linear interpolation but with the constants chosen in a way that minimizes relative error. We show that by placing certain constraints on the errors at three points within each interpolation interval, relative errors are greatly reduced. The implementation-targets are large FPGAs that have in-built multipliers, adders, and distributed memory.
    Original languageEnglish
    Title of host publicationAdvances in Computer Systems Architecture
    Subtitle of host publication11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006. Proceedings
    EditorsChris Jesshope, Colin Egan
    Place of PublicationBerlin
    PublisherSpringer
    Pages6-23
    Number of pages18
    ISBN (Electronic)978-3-540-40058-5
    ISBN (Print)978-3-540-40056-1
    DOIs
    Publication statusPublished - Sep 2006
    Event11th Asia-Pacific Conference, Asia-Pacific Conference on Advances in Computer Systems Architecture 2006 - Shanghai, China
    Duration: 6 Sep 20068 Sep 2006
    Conference number: 11th

    Conference

    Conference11th Asia-Pacific Conference, Asia-Pacific Conference on Advances in Computer Systems Architecture 2006
    CountryChina
    CityShanghai
    Period6/09/068/09/06

    Fingerprint Dive into the research topics of 'Implementation of square-root and exponential functions for large FPGAs'. Together they form a unique fingerprint.

    Cite this