OpenMP on the low-power TI keystone II ARM/DSP system-on-chip

Eric Stotzer; Ajay Jayaraj; Murtaza Ali; Arnon Friedmann; Gaurav Mitra; Alistair P. Rendell; Ian Lintault

doi:10.1007/978-3-642-40698-0_9

OpenMP on the low-power TI keystone II ARM/DSP system-on-chip

Eric Stotzer, Ajay Jayaraj, Murtaza Ali, Arnon Friedmann, Gaurav Mitra, Alistair P. Rendell, Ian Lintault

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

26 Citations (Scopus)

Abstract

The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operations per second (FLOPS) per Watt, if used efficiently. This paper reports an initial attempt at developing a bare-metal OpenMP runtime for the C66X multi-core DSP using the Open Event Machine RTOS. It also outlines an extension to OpenMP that allows code to run across both the ARM and the DSP cores simultaneously. Preliminary performance data for OpenMP constructs running on the ARM and DSP parts of the SoC are given and compared with other current processors.

Original language	English
Title of host publication	OpenMP in the Era of Low Power Devices and Accelerators - 9th International Workshop on OpenMP, IWOMP 2013, Proceedings
Pages	114-127
Number of pages	14
DOIs	https://doi.org/10.1007/978-3-642-40698-0_9
Publication status	Published - 5 Sept 2013
Externally published	Yes
Event	9th International Workshop on OpenMP in the Era of Low Power Devices and Accelerators, IWOMP 2013 - Canberra, ACT, Australia Duration: 16 Sept 2013 → 18 Sept 2013

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	8122 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	9th International Workshop on OpenMP in the Era of Low Power Devices and Accelerators, IWOMP 2013
Country/Territory	Australia
City	Canberra, ACT
Period	16/09/13 → 18/09/13

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10.1007/978-3-642-40698-0_9Licence: In Copyright

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Stotzer, E., Jayaraj, A., Ali, M., Friedmann, A., Mitra, G., Rendell, A. P., & Lintault, I. (2013). OpenMP on the low-power TI keystone II ARM/DSP system-on-chip. In OpenMP in the Era of Low Power Devices and Accelerators - 9th International Workshop on OpenMP, IWOMP 2013, Proceedings (pp. 114-127). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 8122 LNCS). https://doi.org/10.1007/978-3-642-40698-0_9

Stotzer, Eric ; Jayaraj, Ajay ; Ali, Murtaza et al. / OpenMP on the low-power TI keystone II ARM/DSP system-on-chip. OpenMP in the Era of Low Power Devices and Accelerators - 9th International Workshop on OpenMP, IWOMP 2013, Proceedings. 2013. pp. 114-127 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "The Texas Instrument (TI) Keystone II architecture integrates an octa-core C66X DSP with a quad-core ARM Cortex A15 MPCore processor in a non-cache coherent shared memory environment. This System-on-a-Chip (SoC) offers very high Floating Point Operations per second (FLOPS) per Watt, if used efficiently. This paper reports an initial attempt at developing a bare-metal OpenMP runtime for the C66X multi-core DSP using the Open Event Machine RTOS. It also outlines an extension to OpenMP that allows code to run across both the ARM and the DSP cores simultaneously. Preliminary performance data for OpenMP constructs running on the ARM and DSP parts of the SoC are given and compared with other current processors.",

author = "Eric Stotzer and Ajay Jayaraj and Murtaza Ali and Arnon Friedmann and Gaurav Mitra and Rendell, {Alistair P.} and Ian Lintault",

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Stotzer, E, Jayaraj, A, Ali, M, Friedmann, A, Mitra, G, Rendell, AP & Lintault, I 2013, OpenMP on the low-power TI keystone II ARM/DSP system-on-chip. in OpenMP in the Era of Low Power Devices and Accelerators - 9th International Workshop on OpenMP, IWOMP 2013, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 8122 LNCS, pp. 114-127, 9th International Workshop on OpenMP in the Era of Low Power Devices and Accelerators, IWOMP 2013, Canberra, ACT, Australia, 16/09/13. https://doi.org/10.1007/978-3-642-40698-0_9

OpenMP on the low-power TI keystone II ARM/DSP system-on-chip. / Stotzer, Eric; Jayaraj, Ajay; Ali, Murtaza et al.

OpenMP in the Era of Low Power Devices and Accelerators - 9th International Workshop on OpenMP, IWOMP 2013, Proceedings. 2013. p. 114-127 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 8122 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Stotzer E, Jayaraj A, Ali M, Friedmann A, Mitra G, Rendell AP et al. OpenMP on the low-power TI keystone II ARM/DSP system-on-chip. In OpenMP in the Era of Low Power Devices and Accelerators - 9th International Workshop on OpenMP, IWOMP 2013, Proceedings. 2013. p. 114-127. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-40698-0_9

OpenMP on the low-power TI keystone II ARM/DSP system-on-chip

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